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Journal / Archives / Electronics & Communication / VDW-2026-355B83C
Electronics & Communication

AI-Driven Fault Detection and Power Optimization in VLSI Circuits Using Machine Learning Techniques

Sushovan Chandra Susmita Bhaskar Barsha Maity
Dr Sudhir Chandra Sur Institute of Technology and Sports Complex Published: 15 June 2026 Vol. 1, Issue 1 — pp. 4–8 116 views
Abstract

The proposed FPGA-based architecture was conceptually evaluated against conventional CPU and GPU platforms across three key metrics: power consumption, inference throughput, and energy efficiency. FPGAs demonstrate significantly lower power consumption compared to GPUs while maintaining competitive inference throughput suitable for real-time edge applications. The architecture achieves superior performance-per-watt, making it highly suitable for resource-constrained embedded environments such as IoT devices, autonomous systems, and smart healthcare applications. Dynamic voltage-frequency scaling further reduces power consumption during low-workload periods, while quantization and pruning techniques maintain model accuracy within acceptable bounds for edge deployment.

Keywords
FPGA Edge Computing Deep Learning Inference Energy Efficiency Neural Network Acceleration Hardware Acceleration
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How to Cite
Sushovan Chandra, Susmita Bhaskar & Barsha Maity (2026). AI-Driven Fault Detection and Power Optimization in VLSI Circuits Using Machine Learning Techniques. Volume of International Discoveries and Youth Academic Works, Achievements, and Novelties - VIDYAWAN, 1(1), 4–8. https://doi.org/doi.org/10.5281/zenodo.20703839

Cited via DOI — this article is permanently archived on Zenodo.